i7iXdZddlZddlmZmZmZmZmZmZddl m Z m Z m Z m Z mZmZmZmZmZgdZGddeZGdd eZGd d eZy) z pygments.lexers.hdl ~~~~~~~~~~~~~~~~~~~ Lexers for hardware descriptor languages. :copyright: Copyright 2006-2025 by the Pygments team, see AUTHORS. :license: BSD, see LICENSE for details. N) RegexLexerbygroupsincludeusingthiswords) TextCommentOperatorKeywordNameStringNumber Punctuation Whitespace) VerilogLexerSystemVerilogLexer VhdlLexerceZdZdZdZddgZdgZdgZdZdZ dZ d e jd fd e fd eej e fd e j"fde j$fdefdedfdej(fdej,fdej,fdej.fdej0fdej2fdej4fdefdej2fdefdefdej:fdee ej>e fdee ej>e d fe!d!d"#efe!d$d%d"&e jfe!d'd(d"&ejDfe!d)d"#ejFfd*ejHfd+efd,efgd-ed.fd/ej fd0efd eej e fd1efgd2e jfd3e j$fd4e j"d.fd5e jfd6e jfd7e d.fgd8ej>d.fgd9Z%d:Z&y;)/-] [()\[\],.;\'] `[a-zA-Z_]\w*^(\s*)(package)(\s+)^(\s*)(import)(\s+)import)qalways always_comb always_ff always_latchandassign automaticbeginbreakbufbufif0bufif1casecasexcasezcmosconstcontinuedeassigndefaultdefparamdisabledoedgeelseendendcase endfunction endgenerate endmodule endpackage endprimitive endspecifyendtableendtaskenumeventfinalforforceforeverforkfunctiongenerategenvarhighz0highz1ifinitialinoutinputintegerjoinlarge localparam macromodulemediummodulenandnegedgenmosnornotnotif0notif1oroutputpacked parameterpmosposedge primitivepull0pull1pulldownpulluprcmosrefreleaserepeatreturnrnmosrpmosrtranrtranif0rtranif1scalaredsignedsmallspecify specparamstrengthr strong0strong1structtabletasktrantranif0tranif1typetypedefunsignedvarvectoredvoidwaitweak0weak1whilexnorxor\bsuffix) accelerateautoexpand_vectornets celldefinedefault_nettyperBelsif endcelldefineendif endprotect endprotectedexpand_vectornetsifdefifndefr noacceleratenoexpand_vectornetsnoremove_gatenamesnoremove_netnamesnounconnected_driveprotect protectedremove_gatenamesremove_netnamesresetall timescaleunconnected_driveundef`)prefixr)4bits bitstorealbitstoshortreal countdriversdisplayfclosefdisplayfinishfloorfmonitorfopenfstrobefwrite getpatternhistoryincsaver\itorkeylistlogmonitor monitoroff monitoronnokeynologprinttimescalerandomreadmembreadmemhrealtime realtobitsreset reset_count reset_valuerestartrtoisavescalescopeshortrealtobits showscopes showvariablesshowvars sreadmemb sreadmemhstimestopstrobetime timeformatwritez\$)byteshortintintlongintr]rbitlogicregsupply0supply1tritriandtriortri0tri1trireguwirewirewand worshortrealrealr[a-zA-Z_]\w*:(?!:)\$?[a-zA-Z_]\w*\\(\S+)"#pop/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3}) [^\\"\n]+\\[^/\n]+/[*](.|\n)*?[*]/z//.*?\n/ (?<=\\)\n\n [\w:]+\*?rootr rr)c@d}d|vr|dz }d|vr|dz }d|vr|dz }|S)z`Verilog code will use one of reg/wire/assign for sure, and that is not common elsewhere.rrg?rr/)textresults \/mnt/ssd/data/python-lab/ChefSystem/venv/lib/python3.12/site-packages/pygments/lexers/hdl.py analyse_textzVerilogLexer.analyse_texts? D= cMF T> cMF t  cMF N)'__name__ __module__ __qualname____doc__namealiases filenames mimetypesurl version_added_wsr PreprocrrrEscapeSingle MultilinerCharrFloatHexBinIntegerOctr r Constantr Namespacer rBuiltinTypeLabeltokensrrrrrrs D#GI!"I 1CM )CW__g 6 Z (6==*= > -w~~ > .0A0A B  $ VX & Dfkk R 5v|| D -v|| < *FJJ 7 #VZZ 0 $fnn 5 $fjj 1 & ! &.. ) !8 , { + t}} - $hz7;L;Ld&S T #Xj':K:KT%R  :"CH#I$% ("&e5__ WU ,\\ 1:? @ \\   #DJJ /  &  WL \66 " ? O 6 " (6==*= > FO   ) '"3"3 4  0 7?? # 7?? + J '  4>>6 2 {`FD rrc eZdZdZdZddgZddgZdgZdZdZ d Z gd e e e jd fd e e ej e fd e e ej e dfde fde ej$e fde j&fde j(fdefdedfdej,fdej0fdej0fdej2fdej4fdej6fdej8fdefdej6fdefed d!"ej>fd#efd$e jBfed%d!"efd&e ejDe e jFfd'e ejDe e jFfd(e ejDe ee e jFfed)d!"ejHfed*d!"e jfed+d!"e jJfd,e jLfd-e fd.e fd/ed0fd1ej$fd2efde ej$e fd3efgd4e jfd5e j(fd6e j&d0fd7e jfd8e jfd9e d0fgd:e j d0fgd;Z'y<)=rzi Extends verilog lexer to recognise all SystemVerilog keywords from IEEE 1800-2009 standard. systemverilogsvz*.svz*.svhztext/x-systemverilogz+https://en.wikipedia.org/wiki/SystemVerilog1.5rz^(\s*)(`define)rr'r(r)rrrrrrr r!r"r#z4([1-9][_0-9]*)?\s*\'[sS]?[bB]\s*[xXzZ?01][_xXzZ?01]*z6([1-9][_0-9]*)?\s*\'[sS]?[oO]\s*[xXzZ?0-7][_xXzZ?0-7]*z6([1-9][_0-9]*)?\s*\'[sS]?[dD]\s*[xXzZ?0-9][_xXzZ?0-9]*zB([1-9][_0-9]*)?\s*\'[sS]?[hH]\s*[xXzZ?0-9a-fA-F][_xXzZ?0-9a-fA-F]*z \'[01xXzZ]z [0-9][_0-9]*r$)insidedistrrz[()\[\],.;\'$]r&) accept_onaliasr*r+r,r-r.assertr/assumer0beforer1bindbinsbinsofr2r3r4r5r6r7r8cellcheckerclockingr9config constraintcontextr;cover covergroup coverpointcrossr<r=r>designr?r@rArBrCrD endchecker endclocking endconfigrErFendgroup endinterfacerGrHrI endprogram endproperty endsequencerJrKrLrM eventuallyexpectexportexternrO first_matchrPrQforeachrRrSforkjoinrTrUrVglobalrWrXrYiffifnone ignore_bins illegal_binsimplies implementsr)incdirrrZr[r\instance interconnect interface intersectr^join_any join_noner_letliblistlibrarylocalr`ramatchesrbmodportrcrdrenettypenewnexttimerfrgnoshowcancelledrhrirjnullrkrlpackagermrnrorprqpriorityprogrampropertyrrrrsrtrupulsestyle_ondetectpulsestyle_oneventpurerandrandcrandcase randsequencervrw reject_onrxryrestrictrzr{r|r}r~rs_always s_eventually s_nexttimes_until s_until_withrsequence showcancelledrsoftsolverrstaticstrongrrrsupersync_accept_onsync_reject_onrtaggedrr throughout timeprecisiontimeunitrrrrunionuniqueunique0until until_withuntypeduservirtualr wait_orderweakrrrwildcardwithwithinrrz(class)(\s+)([a-zA-Z_]\w*)z(extends)(\s+)([a-zA-Z_]\w*)z,(endclass\b)(?:(\s*)(:)(\s*)([a-zA-Z_]\w*))?)!rrchandler:rNrr]rrrrrr shortrealrr rrrrrrrrrrrrrrrrwor)z `__FILE__z `__LINE__z`begin_keywordsz `celldefinez`default_nettypez`definez`elsez`elsifz `end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz `resetallz `timescalez`unconnected_drivez`undefz `undefineall)z$exitz$finishz$stopz $realtimez$stimez$timez$printtimescalez $timeformatz $bitstorealz$bitstoshortrealz$castz$itorz $realtobitsz$rtoiz$shortrealtobitsz$signedz $unsignedz$bitsz $isunboundedz $typenamez $dimensionsz$highz $incrementz$leftz$lowz$rightz$sizez$unpacked_dimensionsz$acosz$acoshz$asinz$asinhz$atanz$atan2z$atanhz$ceilz$clog2z$cosz$coshz$expz$floorz$hypotz$lnz$log10z$powz$sinz$sinhz$sqrtz$tanz$tanhz $countbitsz $countonesz $isunknownz$onehotz$onehot0z$infoz$errorz$fatalz$warningz$assertcontrolz$assertfailoffz $assertfailonz $assertkillz$assertnonvacuousonz $assertoffz $assertonz$assertpassoffz $assertpassonz$assertvacuousoffz$changedz $changed_gclkz$changing_gclkz $falling_gclkz$fellz $fell_gclkz $future_gclkz$pastz $past_gclkz $rising_gclkz$rosez $rose_gclkz$sampledz$stablez $stable_gclkz $steady_gclkz$coverage_controlz $coverage_getz$coverage_get_maxz$coverage_mergez$coverage_savez $get_coveragez$load_coverage_dbz$set_coverage_db_namez$dist_chi_squarez $dist_erlangz$dist_exponentialz $dist_normalz $dist_poissonz$dist_tz $dist_uniformz$randomz$q_addz$q_examz$q_fullz $q_initializez $q_removez$async$and$arrayz$async$and$planez$async$nand$arrayz$async$nand$planez$async$nor$arrayz$async$nor$planez$async$or$arrayz$async$or$planez$sync$and$arrayz$sync$and$planez$sync$nand$arrayz$sync$nand$planez$sync$nor$arrayz$sync$nor$planez$sync$or$arrayz$sync$or$planez$systemz$displayz $displaybz $displayhz $displayoz$monitorz $monitorbz $monitorhz $monitoroz $monitoroffz $monitoronz$strobez$strobebz$strobehz$strobeoz$writez$writebz$writehz$writeoz$fclosez $fdisplayz $fdisplaybz $fdisplayhz $fdisplayoz$feofz$ferrorz$fflushz$fgetcz$fgetsz $fmonitorz $fmonitorbz $fmonitorhz $fmonitoroz$fopenz$freadz$fscanfz$fseekz$fstrobez $fstrobebz $fstrobehz $fstrobeoz$ftellz$fwritez$fwritebz$fwritehz$fwriteoz$rewindz$sformatz $sformatfz$sscanfz$swritez$swritebz$swritehz$swriteoz$ungetcz $readmembz $readmemhz $writemembz $writememhz$test$plusargsz$value$plusargsz$dumpallz $dumpfilez $dumpflushz $dumplimitz$dumpoffz$dumponz $dumpportsz $dumpportsallz$dumpportsflushz$dumpportslimitz $dumpportsoffz $dumpportsonz $dumpvarsrrrrrrrrrrz//.*?$r r r r r N)(rrrrrrrrrrr rrr r!r r,rr"r#r$rr%rr&r(r*r)r'r rWordr r+ DeclarationClassr.r-r/r0rrrrrsA D%G!I'(I 7CM )C} *goo!F P} $hz7;L;Lj&Y Z} $Xj':K:KZ%XZb c} Z } (6==*= > } .w~~ >} /0A0A B}  $} VX &} Efkk R} 6v|| D} .v|| <} E ZZ !} $G ZZ %} (G ^^ )} ,S ZZ -} 2F #3} 4fnn -5} 8"8 ,9} :%e 4hmm D;} > ,?} @t}} -A} D(RS)TU* E} \+ g)):tzz B D]} `- g)):tzz B Da} d= g)):{JPTPZPZ [ ]e} j@ \\ k} BN  __ C} TMZ [M!\\\]N U} t#DJJ /u} v  &w} x y} ~66 " ? O 6 " (6==*= > FO   ) '"3"3 4  / 7?? # 7?? + J '  4>>6 2 ]QFrrceZdZdZdZdgZddgZdgZdZdZ e je jzZ defd eej"efd ej&fd ej(fd ej*fd efdej0fdefdefdeeeej6fdeeeefdeeeej6efdeeeej6fdeej6ej6feddej6fdeeeej:fdeeeej:eeeej:ee fdeej:eeefdeeeedfe de de d d!efge dd!ej:fdefd"ed#fged$dejBfged%defgd&e"jFfd'e"jFfd(e"jHfd)e"jJfd*e"jLfd+e"jNfgd,Z(y-).rz For VHDL source code. vhdlz*.vhdlz*.vhdz text/x-vhdlz"https://en.wikipedia.org/wiki/VHDLr4rrz--.*?$rz'(U|X|0|1|Z|W|L|H|-)'r$z '[a-z_]\w*r%z "[^\n\\"]*"z(library)(\s+)([a-z_]\w*)z(use)(\s+)(entity)z(use)(\s+)([a-z_][\w.]*\.)(all)z(use)(\s+)([a-z_][\w.]*)z(std|ieee)(\.[a-z_]\w*))stdieeeworkrrz"(entity|component)(\s+)([a-z_]\w*)zN(architecture|configuration)(\s+)([a-z_]\w*)(\s+)(of)(\s+)([a-z_]\w*)(\s+)(is)z ([a-z_]\w*)(:)(\s+)(process|for)z (end)(\s+)endblocktypeskeywordsnumbersz [a-z_]\w*;r)booleanr characterseverity_levelr]r delay_lengthnaturalpositiver bit_vectorfile_open_kindfile_open_status std_ulogicstd_ulogic_vector std_logicstd_logic_vectorrr)_absaccessafterr8allr. architecturearrayr9 attributer1blockbodybufferbusr6 component configurationconstant disconnectdowntorBrrCentityexitfilerPrTrUgenericgroupguardedrYimpureininertialr[islabelrilinkageliteralloopmapmodrdrnnextrgrhrqofonopenrkothersoutrrport postponed procedureprocessrxrangerecordregisterrejectremrzrolrorselectseveritysignalsharedslasllsrasrlsubtypethento transportrunitsrrvariablerwhenrrrrz\d{1,2}#[0-9a-f_]+#?z\d+z(\d+\.\d*|\.\d+|\d+)E[+-]?\d+z X"[0-9a-f_]+"z O"[0-7_]+"z B"[01_]+")rrrrrN))rrrrrrrrrrre MULTILINE IGNORECASEflagsrrrr"r r#r$r%r r Attributerr r,rrrrrr.rr)r&r'r*r(r0rrrrrus DhG7#II .CM LL2== (EZ (6==*= >  ' .0A0A B %v{{ 3 !8 , DNN + { + V $ ) gz4>> : < "HWj'$J K / gz4>>7 C E ( gz4>> : < ' dnndnn 5 7 *5 9 ^^  2 gz4:: 6 8. gz4::z7Jjj*g7 81 djj(J @ B HU4[*=z J G  J  I  4 I% N J  4:: & Z ; '  GPU V \\   0 9>!?"#  *%fnn 5 V^^ $ -v|| < vzz * FJJ ' 6:: &  SQFrr)rrpygments.lexerrrrrrrpygments.tokenr r r r r rrrr__all__rrrrrrrsW LL$$$ >{:{|``F] ]r